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radar receive path afe: 4 - channel mux with lna, pga, aaf, and adc data sheet AD8284 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibili ty is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any pa tent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 ana log devices, inc. all rights reserved. technical support www.analog.com features 4 - channel mux to lna, pga, aaf 1 direct - to - adc channel programmable gain amplifier (pga) includes low noise preamplifier (lna) spi - programmable gain = 17 db to 35 db in 6 db steps antialiasing filter (aaf) programmable third - order low - pass elliptic filter (lpf) from 9 mhz to 15 mhz analog - to - digital converter (adc) 12 bits of accuracy of up to 80 msps snr = 67 db sfdr = 68 dbc low powe r, 3 45 mw at 12 bits per 80 msps low nois e, 3.5 nv/hz maximum of input referred voltage noise power - down mode 64 - lead, 10 mm 10 mm tqfp package specified from ?40 c to +105c qualified for automotive applications applications automotive radar adaptive cruise control collision avoidance blind spot detection self parking electronic bumper functional block dia gram figure 1. general description the AD8284 is an integrated analog front end designed for low cost, compact size, flexibility, and ease of use. it contains a 4 - chan - nel differential multiplexer ( mux ), a 1 - channel low noise preamplifier (lna) with a programmable gain amplifier (pga) and an antialiasing filter (aaf) , as well as one direct - to - adc channel, all integrated with a single , 12 - bit anal og - to - digital converter (adc). the AD8284 also inco rporates a saturation detection circui t for high frequency over voltage conditions that would otherwise be filtered by the aaf. the analog channel features a gain range of 17 db to 35 db in 6 db increments , and an adc with a conversi on rate of up to 80 msps. the combined input referred voltage noise of the entire channel is 3.5 nv/hz at maximum gain. the channel is optimized for dynamic performance and low power in applications where a small package size is critical. fabricated in a n advanced cmos process, the AD8284 is available in a 10 mm 10 mm, rohs compliant, 64 - lead tqfp. it is speci - fied over the automotive temperature range of ?40c to +105c. ina+ ina? inb+ inc+ inc? inb? ind+ ind? inadc+ inadc? cs sclk sdo sdi aux clk+ clk? zsel pdwn sflag avdd33 rbias vref dvdd33x dvdd18 spi avdd18 AD8284 saturation detection mux[1] to mux[0] reference d0 t o d1 1 12-bit adc mux lna mux pga aaf 10992-001
AD8284 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac specifications .......................................................................... 3 digital specifications ................................................................... 5 switching specifications .............................................................. 6 abso lute maximum ratings ....................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 12 radar receive path afe ............................................................ 12 channel overview ...................................................................... 13 adc ............................................................................................. 15 aux channel .............................................................................. 15 clock input considerations ...................................................... 15 clock duty cycle considerations ............................................ 16 clock jitter considerations ....................................................... 16 sdi and sdo pins ...................................................................... 16 sclk pin ..................................................................................... 16 cs pin ........................................................................................... 16 rbias pin .................................................................................... 16 voltage reference ....................................................................... 16 power and ground recommendations ................................... 16 exposed pad thermal heat slug recommendations ............ 17 serial port interface (spi) .............................................................. 18 hardware interface ..................................................................... 18 memory map .................................................................................. 20 reading the memory map table .............................................. 20 logic levels ................................................................................. 20 reserved locations .................................................................... 20 default values ............................................................................. 20 application circuits ....................................................................... 24 packaging and ordering information ......................................... 26 outline dimensions ................................................................... 26 ordering guide .......................................................................... 26 automotive products ................................................................. 26 revision history 7 /13 rev. a to rev. b changes to input resistance and power - down dissipation parameters; table 1 ........................................................................... 3 updated outline dimensions ....................................................... 26 chang es to ordering guide .......................................................... 26 1 /1 3 rev. 0 to rev. a changes to figure 16 ...................................................................... 14 10/ 12 rev ision 0: initial version
data sheet AD8284 rev. b | page 3 of 28 specifications ac specifications avdd18x = 1.8 v, avdd33x = 3.3 v, dvdd18x = 1.8 v, dvdd33x = 3.3 v, 1.0 v internal adc reference, f in = 2.5 mhz, f s = 80 msps , r s = 50 ?, lna + pga gain = 35 db , lpf cutoff = f samplech /4, 12 - bit operation, temperature = ? 40 c to +105 c, all specifications guaranteed by testing, unless otherwise noted. table 1 . parameter 1 test conditions/comments min typ max unit analog channel characteristics lna, pga, and aaf channel gain programmable 17/23/29/35 db gain range 18 db gain error ?1.25 +1.25 db input voltage range 2 channel gain = 17 db 0.283 v p -p channel gain = 23 db 0.142 v p -p channel gain = 29 db 0.071 v p -p channel gain = 35 db 0.036 v p -p input resistance 200 input impedance 0.2 00 0.265 0. 300 k 200 k input impedance 160 200 240 k input capacitance 2 7 pf input referred voltage noise 2 maximum gain at 1 mhz 1.85 nv/hz minimum gain at 1 mhz 6.03 nv/hz noise figure 2 maximum gain, r s = 50 , not terminated 7.1 db maximum g ain, r s = r in = 50 12.7 db output offset gain = 17 db ?60 +60 lsb gain = 35 db ?250 +250 lsb aaf low - pass filter cutoff ?3 db, programmable 9.0 to 15.0 mhz tolerance after filter autotune ?10 5 +10 % aaf attenuation in stop band 2 third - order elliptic filter 2 cutoff 30 db 3 cutoff 40 db group delay variation 2 filter set at 9 mhz 400 ns 1 db compression 2 relative to output 11.9 dbm saturation flag response time time between saturation event and satura tion flag going high (1 db over drive) 30 100 ns time between end of saturation event and saturation flag going low 25 40 ns saturation flag accuracy gain = 29 db off f or pga voltages below 2 v p -p 2 v p -p on f or pga voltages above 2.25 v p -p 2.25 v p -p m ux 2 on r esistance 50 switching t ime 200 ns power supply avdd18x 2 1.7 1.8 1.9 v avdd33x 2 3.1 3.3 3.5 v dvdd18x 2 1.7 1.8 1.9 v dvdd33x 2 3.1 3.3 3.5 v i avdd18 f s = 60 msps 54 ma i avdd33 f s = 60 msps 65 ma i dvdd18 f s = 60 msps 15 ma i dvdd33 f s = 60 msps 2 ma total power dissipation no signal, typical supply voltage maximum supply current; e xcludes output current 345 mw
AD8284 data sheet rev. b | page 4 of 28 parameter 1 test conditions/comments min typ max unit power - down dissipation t a = ? 25 c to +105 c 2.5 4.0 mw t a = ? 40 c to +2 5 c 2.5 8.0 mw power supply rejection ratio (psrr) 2 relative to input 1.6 mv/v adc resolution 2 12 bits maximum sample rate 80 msps signal - to - noise ratio (snr) f in = 1 mhz 67 db signal - to - noise - and - distortion ratio (sinad) 2 66 db snrfs 2 68 db differential nonlinearity (dnl) guaranteed no missing codes 1 lsb integral nonlinearity (inl) f s = 60 msps 4 10 lsb f s = 80 msps 17 lsb effective number of bits (enob) 2 10.67 lsb adc output characteristics 2 maximum cap acitor load per bit 20 pf i dvdd33 peak current with cap acitor load 2 peak current per bit when driving a 20 p f load; can be programmed via the spi port , if required 40 ma adc reference output voltage error vref = 1.000 v 20 mv load regulation at 1.0 ma, vref = 1.000 v 2 mv current output ?1 +1 ma input resistance 6 k full channel characteristics lna, pga, aaf, and adc snrfs f in = 1 mhz, ? 10 dbfs output gain = 17 db, f s = 60 msps 60 64 dbfs gain = 23 db, f s = 60 msps 60 64 dbfs gain = 29 db, f s = 60 msps 60 64 dbfs gain = 35 db, f s = 60 msps 60 64 dbfs gain = 17 db, f s = 80 msps 45 62 dbfs sinad 2 f in = 1 mhz gain = 17 db 62 db gain = 23 db 63 db gain = 29 db 64 db gain = 35 db 63 db spurious - free dynamic range ( sfdr ) f in = 1 mhz, ?10 dbfs output gain = 17 db, f s = 60 msps 62 68 dbc gain = 23 db, f s = 60 msps 62 68 dbc gain = 29 db, f s = 60 msps 62 68 dbc gain = 35 db, f s = 60 msps 62 71 dbc gain = 17 db, f s = 80 msps 45 62 dbc harmonic distortion 2 f in = 1 mhz at ?10 dbfs output second harmonic gain = 17 db ?70 dbc g ain = 35 db ?70 dbc third harmonic g ain = 17 db ?66 dbc g ain = 35 db ?75 dbc im3 distortion f in1 = 1 mhz, f in2 = 1.1 mhz, ?1 dbfs , gain = 35 db ?69 dbc gain response time 600 ns overdrive recovery time 200 ns 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and testing methodology. 2 guaranteed by design only.
data sheet AD8284 rev. b | page 5 of 28 digital specificatio ns avdd18x = 1.8 v, avdd33 x = 3.3 v, dvdd18 x = 1.8 v, dvdd33 x = 3.3 v, 1.00 v internal adc reference, f in = 2.5 mhz, f s = 80 msps, r s = 50 ?, lna + pga gain = 35 db , lpf cutoff = f samplech /4, 12 - bit operation, temperature = ? 40 c to +105 c, all specification s guaranteed by testing, unless otherwise noted. table 2 . parameter 1 temperature min typ max unit clock inputs (clk+, clk?) 2 logic compliance cmos/lvds/lvpecl differential input voltage 3 full 250 mv p -p input common - mode voltage full 1.2 v input resistance (differential) 25c 20 k input capacitance 25c 1.5 pf logic inputs (pdwn, sclk, aux, mux [ 0 ] , mux [ 1 ] , zsel) 2 logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 30 k input capacitance 25c 0.5 pf logic input ( cs ) 2 logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 70 k input capacitance 25c 0.5 pf logic input (sdi) 2 logic 1 voltage full 1.2 dvdd33x + 0.3 v logic 0 voltage full 0 0.3 v input resistance 25c 30 k input capacitance 25c 2 pf logic output (sdo) logic 1 voltage (i oh = 800 a) full 3.0 v logic 0 voltage (i ol = 50 a) full 0.3 v logic output s (d 11 to d0 , sflag) logic 1 voltage (i oh = 2 ma) full 3.0 v logic 0 voltage (i ol = 2 ma) full 0.3 v 1 see th e an - 835 application note , understanding high speed adc testing and evaluation , for a c omplete set of definitions and testing methodology . 2 guaranteed by design only. 3 specified for lvds and lvpecl only.
AD8284 data sheet rev. b | page 6 of 28 switching specifications avdd18x = 1.8 v, avdd33x = 3.3 v, dvdd18x = 1.8 v, dvdd33x = 3.3 v, 1.00 v internal adc reference, f in = 2.5 mhz, f s = 80 msps, r s = 50 , lna + pga gain = 35 db, lpf cutoff = f samplech /4, 12-bit operation, temperature = ?40c to +105c, unless otherwise noted. all specifications guaranteed by design only. table 3. parameter 1 symbol temperature min typ max unit clock clock rate full 10 80 msps clock pulse width high at 80 msps t eh full 6.25 ns clock pulse width low at 80 msps t el full 6.25 ns clock pulse width high at 40 msps t eh full 12.5 ns clock pulse width low at 40 msps t el full 12.5 ns output parameters propagation delay at 80 msps t pd full 6 ns rise time t r full 1.9 ns fall time t f full 1.2 ns data setup time at 80 msps t ds full 6.2 ns data hold time at 80 msps t dh full 6.0 ns data setup time at 40 msps t ds full 18 ns data hold time at 40 msps t dh full 6 ns pipeline latency full 7 clock cycles 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and testing methodology. timing and switching diagram figure 2. timing definitions for switching specifications n ?1 inax n n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n clk? clk+ d11 to d0 t pd t eh t el t ds t dh 10992-002
data sheet AD8284 rev. b | page 7 of 28 absolute maximum ratings table 4. parameter rating electrical avdd18, avdd18 adc to agnd ?0.3 v to +2.0 v avdd33, avdd33ref to agnd ?0.3 v to +3.9 v dvdd18, dvdd18clk to agnd ?0.3 v to +2.0 v dvdd33clk, dvdd33drv, and dvdd33spi to agnd ?0.3 v to +3.9 v analog inputs inx+, inx? to agnd ?0.3 v to +3.9 v auxiliary inputs inadc+, inadc? to agnd ?0.3 v to +2.0 v digital outputs (d11 to d0, sdo) and sdi to agnd ?0.3 v to +3.9 v clk+, clk? to agnd ?0.3 v to +3.9 v pdwn, sclk, cs , aux, zsel to agnd ?0.3 v to +3.9 v rbias, vref to agnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40c to +105c storage temperature range (ambient) ?65c to +150c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c esd caution stresses abo v ethose listedunderabsolutemaximumratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximumratingconditionsfor extendedperiodsmayaffect de v ice reliability.
AD8284 data sheet rev. b | page 8 of 28 pin configuration and fu nction descriptions figure 3. pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 nc no connection. tie nc to any potential. 2 sflag saturation f lag . 3 pdwn full power - down. a l ogic high on p dwn overrides the spi and powers down the part ; a logic low allows selection through the spi. 4 dvdd18 1.8 v digital supply. 5 sclk serial clock. 6 cs chip select. 7 sdi serial data input. 8 sdo serial data output. 9 aux auxiliary channel. a l ogic high on aux switches the aux c hannel to adc (inadc+/inadc?) . 10 mux[0] digital control for m ux channel selection. 11 mux[1] digital control for m ux channel selection. 12 zsel input impedance select. a l ogic high on zsel overrides the spi and sets the input impedance to 200 k ; a logic low allows selection through the spi. 13 test1 test. do not use the test1 pin; tie test1 to ground. 14 test2 test. do not use the test2 pin; ti e test2 to ground. 15 dvdd33spi 3.3 v digital supply, spi port. 16 nc no connection. tie nc to any potential. 17 nc no connection. tie nc to any potential. 18 avdd18 1.8 v analog supply. 19 avdd33 3.3 v analog supply. 20 ina + positive m ux analog input for channel a. 21 ina ? negative m ux analog input for channel a. 22 inb + positive m ux analog input for channel b. 23 inb ? negative m ux analog input for channel b. pin 1 AD8284 t op view (not to scale) 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 37 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 47 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 nc sflag pdwn dvdd18 sclk sdi sdo cs aux mux[0] mux[1] zsel test1 test2 dvdd33spi nc dvdd33drv d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 dvdd33drv d1 d0 nc nc nc agnd avdd18adc test3 anout apout rbias vref band avdd33ref dvdd33clk clk? clk+ dvdd18clk test4 nc avdd18 nc avdd33 ina+ ina? inb+ inb? inc+ inc? ind+ ind? avdd33 inadc+ inadc? avdd18 nc notes 1. tie the exposed pad on the bottom side to the analog ground plane. 2. nc = no connection. tie nc to any potential. 10992-003
data sheet AD8284 rev. b | page 9 of 28 pin no. mnemonic description 24 inc + posit ive m ux analog input for channel c. 25 inc ? negative m ux analog input for channel c. 26 ind + positive m ux analog input for channel d. 27 ind ? negative m ux analog input for channel d. 28 avdd33 3.3 v analog supply. 29 inadc+ positive analog input for alternate channel (adc only). 30 inadc ? negative analog input for alternate channel (adc only). 31 avdd18 1.8 v analog supply. 32 nc no connection. tie nc to any potential. 33 nc no connection. tie nc to any potential. 34 a gnd ground . 35 avdd18adc 1.8 v analog supply . 36 test3 test. do not use the test3 pin; tie test3 to ground. 37 anout analog output. anout is for debug purposes only. leave anout floating. 38 apout analog output. apout is for debug purposes only. leave apout floating. 39 rbias external r esistor . the rbias pin set s the internal adc core bias current. 40 vref voltage reference input/output. 41 band band gap voltage . band is for debug purposes only . leave band floating. 42 avdd33ref 3.3 v analog supply. 43 dvdd33clk 3.3 v digital supply. 44 clk ? clock input complement. 45 clk+ clock input true. 46 dvdd18clk 1.8 v digital supply . 47 test4 test. do not use the test4 pin; tie test4 to ground. 48 nc no connection. tie nc to any potential. 49 nc no connection. tie nc to any potential. 50 dvdd33drv 3.3 v digital supply . 51 d11 adc data out put (msb). 52 d10 adc data output . 53 d9 adc data output . 54 d8 adc data output . 55 d7 adc data output. 56 d6 adc data output. 57 d5 adc data output . 58 d4 adc data output. 59 d3 adc data output. 60 d2 adc data output. 61 d1 adc data output. 62 d0 adc data output (lsb). 63 dvdd33drv 3.3 v digital supply . 64 nc no connection. tie nc to any potential. ep exposed pad . tie the exposed pad on the bottom side to the analog ground plane.
AD8284 data sheet rev. b | page 10 of 28 typical performance characteristics avdd18x = 1.8 v, avdd33x = 3.3 v , t a = 25c, f s = 80 msps, r in = 200 k , v ref = 1.0 v. figure 4 . channel gain vs. frequency figure 5 . gain histogram (gain = 17 db) figure 6 . gain histogram (gain = 29 db) figure 7 . short - circuit input referred noise vs. frequency figure 8 . filter frequency response figure 9 . short - circuit output referred noise vs. frequency 60 40 20 0 ?20 ?40 ?60 0.1 100 10 1 gain (db) frequency (mhz) 10992-004 35db 29db 23db 17db 210 180 0 30 60 90 120 150 16.8 17.0 17.2 17.4 17.6 number of hits code 10992-005 350 300 0 50 100 150 200 250 28.5 29.1 28.8 29.4 29.7 30.0 number of hits code 10992-006 0 10 0.1 1 10 noise (nv/ hz ) frequency (mhz) 1 2 3 4 5 6 7 8 9 23db 17db 35db 29db 10992-007 30 20 10 0 ?40 ?30 ?20 ?10 1 10 50 gain (db) frequency (mhz) 10992-008 00 08 10 18 20 28 30 38 40 80 88 90 98 a0 a8 b0 b8 c0 0 200 0.1 1 10 noise (nv/ hz ) frequenc y (mhz) 20 40 60 80 100 120 140 160 180 29db 35db 23db 17db 10992-009
data sheet AD8284 rev. b | page 11 of 28 figure 10 . r in vs. frequency figure 11 . noise figure vs. frequency figure 12 . channel offset distribution (gain = 17 db) figure 13 . channel offset distribution (gain = 35 db) 1,000,000 1 10 100 1,000 10,000 100,000 0.01 0.1 1 10 100 impedance (?) frequency (mhz) 10992-010 23db 17db 0 5 10 15 20 25 30 0.1 1 10 noise figure (db) frequenc y (mhz) 35db 29db 10992-0 1 1 80 20 40 60 0 ?60 ?40 ?20 0 60 20 40 number of hits code 10992-012 80 20 40 60 0 ?200 ?100 0 200 100 number of hits code 10992-013
AD8284 data sheet rev. b | page 12 of 28 theory of o peration radar receive path a fe the primary application for the AD8284 is high speed ramp, frequency modulated, continuous wave (hsr - fmcw ) radar requiring baseband signal bandwidths of up to 15 mhz. figure 14 shows a simplified block diagram of an hsr - fmcw radar system. the signal chain requires multiple channels, each of which is routed into a low noi se amplifie r (lna), a programmable gain amplifier (pga), an antialiasing filter (aaf), and an analog - to - digital converter (adc). the AD8284 provides all of these key components in a single 10 mm 10 mm tqfp package. the performance of each component is designed to meet the demands of an hsr - fmcw radar system. some examples of these performance metrics include the lna noise, pga gain range, aaf cutoff characteristics, and adc sample rate and resolution. the AD8284 includes a multiplexer ( mux ) in front of the analog signal chain as a cost - saving alternative to having an afe for each channel. the mux can be switched between active inputs using the mux pins or through the spi port. the AD8284 also includes a saturation detection circuit that indicates when the lna or pga signals are n o longer in the linear region. this feature helps detect fault conditions th at might otherwise be filtered out by the aaf. figure 14 . simplified blo ck diagram, hsr - fmcw radar system p a dsp antenna vco aaf lna AD8284 mux ref. oscillator chirp ramp generator 12-bit adc saturation detection pga 10992-014
data sheet AD8284 rev. b | page 13 of 28 figure 15 . simplified block diagr am channel overview the AD8284 contains a four - input mux , an lna, a pga, and an aaf in the signal path , as shown in figure 15 . the signal chain inp ut impedance can be either 200 or 200 k . the pga has selectable gains that result in channel gains ranging from 17 db to 35 db. the aaf has a three - pole elliptical response with a selectable cutoff frequency from 9 mhz to 15 mhz. the signal path is full y differential throughout to maximize signal swing and reduce even - order distortion. the lna is designed to be driven from either a differential or single - ended signal source. multiplexer the AD8284 has a mult iplexer ( mux ) at the input to switch as many as four differential c hannels into the signal chain. the active mux channel is controlled by the spi port or by usin g the external pins , mux[0] and mux[1]. the relationship between the input code and the selected mux channel is listed in table 6 . table 6 . digital input values to select the active adc channel aux mux[1] mux[0] active channel 1 x x aux 0 0 0 a 0 0 1 b 0 1 0 c 0 1 1 d the external pins are the default method for s electing the active mux channel but the spi register 0x0c can also control the mux . bit 3 of r egister 0x0c s pecifies whether the spi or the external pins control the mux . low noise amplifier good noise performance relies on a proprietary ultralow noise lna at the beginning of the signal chain ; the lna minimizes the noise contributions from the pga and aaf th at are next in the signal chain . th e input impedance can be either 200 or 200 k , the value of which is selected through the spi port or by the zsel pin. the lna supports differential output voltages as high as 5.0 v p - p with positive and negative excursions of 1.25 v from a common - mode voltage of 1.5 v. because the output saturation level is fixed, the channel gain sets the maximum input signal before saturation. low value feedback resistors and the current driving capability of the o utput stage allow the lna to achieve a low input refer red noise voltage of 3.5 nv/hz at a channel gain of 35 db. the use of a fully differential topology and negative feedback minimizes second - order distortion. differential signaling enables smaller swings at each output, further reducing third - order distort ion. recommendation to achieve the best possible noise performance, it is important to match the impedances seen by the positive and negative inputs. matching the impedances ensures that the signal path rejects any common - mode noise. ina+ ina? inb+ inc+ inc? inb? ind+ ind? inadc+ inadc? cs sclk sdo sdi aux clk+ clk? zsel pdwn sflag avdd33 rbias vref dvdd33x dvdd18 spi avdd18 AD8284 saturation detection mux[1] to mux[0] reference d0 t o d1 1 12-bit adc mux lna mux pga aaf 10992-015
AD8284 data sheet rev. b | page 14 of 28 antialiasing filter the aaf uses a combination of poles and zeros to create a third - order elliptic filter. an elliptic filter is used to achieve a sharp roll - off after the cutoff frequency. t his architecture achieves a ? 30 db per o ctave roll - off in the first octave after the cutoff frequency. the filter uses on - chip tuning to trim the internal resistors and capacitor s to set the desired cutoff frequency. the tuning method reduces variations in the cutoff frequency due to standard ic process tolerances of resistors and capacit ors. the default tuning settings for a ?3 db low - pass filter cutoff is 1/3 1.125 the adc sample clock frequency. th is setting can be changed to 1/4 t he adc sample clock frequency. the cutoff can also be scaled from 0.75 to 1. 25 (in 0.0625 increments) times these frequencies through the spi. tuning is normally off and is initiated by the user via the spi port. after the filter is tuned to a specific frequency, it remain s at th at frequency until another tuning sequence is initiated. the tuning process can take up to 2048 clock cycles. the filter defaults to its highest frequen cy setting before it is tuned. to maintain the expected ratio of clock frequency to cutoff frequency, t un e the filter after initial power - up, after reprogramming the filter cutoff scaling via the spi, or after changing the adc sample rate. occasional retuning during an idle time is recommended to compensate for temperature drift. a cut off frequency range of 9 mhz to 15 mhz is possible , for example ? adc clock: 40 mhz ? default tuned cutoff frequency = (40 mhz 3) 1.125 = 15 mhz the a u totune cycle takes sev eral clock cycles to complete. during this time, the mux channels, a to d, are not operational; however, t he aux input can be used during the autotuning cycle. saturation flag the saturation flag function detect s overvoltage conditions that may push the lna or pg a out of their linear region s. the flag is set when the pga output voltage exceeds 2.0 v p - p or the lna output voltage exceeds 4.0 v p - p. this function is particularly useful for detecting saturation events that may be filtered out by the aaf and are , therefore , undetectable by monitoring the adc output. when the saturation flag trip s , it remain s on for a minimum of 25 ns after the saturation event has ended. figure 16 . simplified block diagram of the a nalog channel inx+ inx? mux vmid vmid vmid vmid saturation detection vx adc ? n? n? n? ? n? ? ? 2pf 2pf lna pga aaf +ref ?ref vx +ref ?ref AD8284 10992-016
data sheet AD8284 rev. b | page 15 of 28 adc the AD8284 uses a pipelined adc architecture. the quantized output from each stage is combined into a 12 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operat e on preceding samples. sampling occurs on the rising edge of the clock. the output staging block aligns the data and passes the data to the output buffers. aux channel the AD8284 allows direct access to the ad c when the mux settings are used to select the aux channel . when this channel is selected, the inputs of the adc can be accessed using the inadc+ and inadc ? pins. t o ensure enough headroom for full - scale, differential , 2.0 v p - p input signals , bias t he ina dc pins with a 0.9 v common - mode voltage. clock input consider ations for optimum performance, clock the AD8284 sample clock inputs (clk+ and clk?) with a differential signal. this signal is typically ac - coupled into the clk+ and clk? pins via a trans - former or by using capacitors ; t hese pins are biased internally and require no additional bias. figure 17 shows the preferred method for clocking the AD8284 . a low jitter clock source, such as the valpey fisher oscillator , vfac3 - bhl ( 50 mhz ) , is conver ted from single - ended to differ - ential using an rf transformer. the back - to - back schottky diodes across the secondary transformer limit clock excursions into the AD8284 to approximately 0.8 v p - p differential. t his helps prevent the large voltage swings of the clock from feeding through to other portions of the AD8284 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. figure 17 . transformer - coupled differential clock if a low jitter clock is available, another option is to ac - couple a diff erential pecl or lvds signal to the sample clock input pins as shown in figure 18 and figure 19 . the ad951x/ad952x family of clock drivers offer s excellent jitter performance. figure 18 . differential pecl sample clock figure 19 . differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single - ended cmos signal. in such applications, drive clk+ directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor in parallel with a 39 k? resistor (see figure 20 ). although the clk+ input circuit supply is via pin 46, d vdd1 8clk , this input is designed to withstand input voltages of up to 3.3 v, making the select ion of the logic voltage of the driver very flexible. the ad951x/ad952x family of parts can be used to provide 3.3 v inputs (see figure 21) . in this case, the 39 k? resistor is not needed. figure 20 . single - ended 1.8 v cmos sample clock figure 21 . single - ended 3.3 v cmos sample clock 0.1f 0.1f 0.1f 0.1f schottk y diodes: hsm2812 3.3v 50? 100? clk? clk+ adc AD8284 mini-circuits ? adt1-1w t , 1:1z xfmr vf ac3 out 10992-017 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50? * clk clk * 50? resis t or is optional. clk? clk+ adc AD8284 pec l driver 3.3v out v f ac3 ad951x/ad952x 10992-018 10 0? 0.1f 0.1f 0.1f 0.1f ad951x/ad952x 50? * clk clk * 50? resis t or is optional. clk? clk+ adc AD8284 lvds driver 3.3v out v f ac3 10992-019 0.1f 0.1f 0.1f 39k? 1.8v cmos driver 50? * optiona l 100? 0.1f clk clk * 50? resistor is optional. clk? clk+ adc AD8284 3.3v out vf ac3 ad951x/ad952x 10992-020 0.1f 0.1f cmos driver 3.3v 50? * optiona l 100? 0.1f clk clk * 50? resistor is optional. clk? clk+ adc AD8284 3.3v out vf ac3 0.1f ad951x/ad952x 10992-021
AD8284 data sheet rev. b | page 16 of 28 clock duty cycle con siderations typical high speed adcs use both clock edges to g enerate a variety of internal timing signals. as a result, these adcs may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD8284 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the AD8284 . when the dcs is on, noise and distortion performance are nearly flat for a wide range of duty cycles. however, some appli - cations may require the dcs function to be off. if so, note that the dynamic range performance can be affected when operat ing in this mode. see table 9 f or more details on using this feature. the duty cycle stabilizer uses a delay locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate. clock jitter conside rations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by snr degradation = 20 log 10[1/2 f a t j ] in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter. if undersampling applications are particularly sensitive to jitter. in cases where aperture jitter may affect t he dynamic range of the AD8284 , treat t he clock input as an analog signal . separate p ower supplies for clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. l ow jitter, crystal controlled oscillators make the best clock sources, such as the valpey fisher vfac3 series. if the clock is generated from another type of source by using the sequential steps of gating, dividing, or other methods, it should be retimed b y the original clock during the last step in that sequence . see the an - 501 application note and the an - 756 application note for more information about how jitter perf ormance relates to adcs. sdi and sdo pin s the sdi and sdo pins are required to operate the spi. the sdi pin ha s an internal 30 k? pull - down resistor that pulls this pin low and is 1.8 v and 3.3 v tolerant. the sdo output pin is 3.3 v logic. sclk pin the sc lk pin is required to operate the spi. it has an internal 30 k? pull - down resistor that pulls this pin low and is both 1.8 v and 3.3 v tolerant. cs pin the cs pin is required to operate the spi. it has an internal 70 k? pull - up resistor that pulls this pin high and is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor nominally equal to 10.0 k ? to ground at the rbias pin. using a resistor other than the recommended 10.0 k? resistor for rbias degrades the performance of the device. therefore, it is imperative that at least a 1.0% tolerance on this resistor be used to achieve consistent performance. voltage reference a stable and accurate 0.5 v voltage reference is bui lt into the AD8284 . this is gained up internally by a factor of 2, setting v ref to 1.0 v, which results in a full - scale differential input span of 2.0 v p - p for the adc. v ref is set internally by default, but th e vref pin can be driven externally with a 1.0 v reference to achieve more accuracy. however, the AD8284 is not specified for adc full - scale ranges below 2.0 v p - p. when applying decoupling capacitors to the vre f pin , use ceramic , low esr capacitors. place t hese capacitors close to the reference pin and on the same layer of the pcb as the AD8284 . the vref pin should have both a 0.1 f capacitor and a 1 f capacitor con nected in parallel to the analog ground. these capacitor values are recommended for the adc to properly settle and acquire the next valid sample. power and ground rec ommendations when connecting power to the ad8 284 , it is recommended that two separate 1.8 v supplies and two separate 3.3 v supplies be used: one supply each for analog 1.8 v (avdd18x) , digital 1.8 v (dvdd18x) , analog 3.3 v (avdd33x) , and digital 3.3 v (dvdd33x). if only one supply is available for both analog and digital, for example, avdd18x and dvdd18x, route the supply to avdd18x first and then tap the supply off and isolate it with a ferrite bead or a filter choke preceded by decoupling capacitors for the dvdd18x. the same method is used for the analog and digital 3.3 v supplies. use several decoupling capacitors on all supplies to cover both high and low frequencies. locate t hese capacitors close to the point of entry at the printed circuit board (pcb) level and close to the AD8284 using minimal trace lengths. the 12 power supply pins are separated into four power supply domains, avdd 18, avdd33, dvdd18 , and dvdd33. each pin within a domain must be powered simultaneously , but each domain can be turned o n independently of the other domains. a single pcb ground plane should be sufficient when using the AD8284 . with proper decoupling and smart partitioning of the analog, digital, and clock section s of the pcb , op timum perfor - mance can be easily achieved.
data sheet AD8284 rev. b | page 17 of 28 exposed p ad thermal heat slug recommendations it is required that the exposed pad on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD8284 . mate a n exposed continuous copper pl ane on the pcb to the AD8284 exposed pad, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. t o ma ximize the coverage and adhe sion betw een the device and the pcb , it is recommended that the continuous copper pad be partitioned by overlaying a silk screen or solder mask to divide the copper pad into uniform sections. this partitioning helps to ensure several tie points between the pcb and the device during the reflow process. us ing one continuous plane with no partitions guarantees only one tie point between the AD8284 and the pcb . for more informatio n about packaging and for additional pcb layout examples, see the an - 772 application note .
AD8284 data sheet rev. b | page 18 of 28 serial p ort interface (spi) the AD8284 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. th e spi offers the user added flexibility and customization depending on the application . addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, as documented in the memory map section. detailed operational information can be found in the an - 877 application note , interfacing to high speed adcs via spi . f our pins define the serial port interface, or spi : t he sclk, sdi, sdo, and cs pins. the serial clock pin (sclk ) synchronize s the read and write data presented to the device. the serial data input and output pins, sdi and sdo, allow data to be sent to and read from the internal memory map registers of the device . the chip select pin ( cs ) is an active low control that enables or disables the read and write cycles (see table 7 ). table 7 . serial port interface pins pin function sclk serial clock. the serial shift clock input. sclk is used to synchronize serial interface reads and writes. sdi serial data input. sdo serial data output . cs chip select (active low). this control gates the read and write cycles. the falling edge of cs , in conjunction with the rising edge of sclk , determines the start of the f raming sequence. during an instruc tion phase, a 16 - bit instruction is transmitted , followed by one or more data bytes, which is determined by bit field w0 and bit field w1. see figure 22 and table 8 for a n example of the serial timing and its definitions . in normal operation, cs signal s to the device that spi commands are about to be received and processed. when cs is brought low, the device processes sclk and sdi to process instructions. normally, cs remains low until the comm unication cycle is complete. however, if the AD8284 is connected to a slow device, cs can be brought high between bytes, allowing older microcontrollers enough time to transfer data into the shift registers. cs can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until cs is taken high to end the communication cycle. this allows complete memory transfers without the need to provide additional instruct ions. regardless of the mode, if cs is taken high in the middle of any byte transfer, the spi state machine is reset and the device waits for a n ew instruction. in addition to the operation modes, the spi port can be configured to operate in different manners. for applications that do not require a control port, the cs line can be tied and held high. this places the remainder of t he spi pins in their secondary mode as defined in the an - 877 application note , interfacing to high speed adcs via spi . cs can also be tied low to enable 3 - wire mode. when cs is tied low, sclk, sdo , and sdi are the only pins required for communication. although the device is synchronized during power - up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the cs line. when operating in 3 - wire mode, it is recommended that a a 1 - , 2 - , or 3 - byte transfer be used exclusively. without an active cs line, streaming mode can be entered but not exited. data can be sent in msb - first or lsb - first mode. msb - first mode is the default at power - up and can be changed by adjusting the configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high spee d adcs via spi . hardware interface the pins described in table 7 constitute the physical interface between the users programming device and the serial port of the AD8284 . the sclk, sdi , and cs pins function as inputs when using the spi interface. the sdo pin is an output during readback. this interface is flexible enough to be controlled by either serial - p rogrammable read - only memory ( prom ) or pic micro - controlle rs. this provides the user with alternative me ans , other than a full spi controller, for programming the device (see the an - 812 application note ).
data sheet AD8284 rev. b | page 19 of 28 figure 22. serial timing details table 8. serial timing definitions parameter minimum timing (ns) description t ds 5 setup time between the data and the rising edge of sclk. t dh 2 hold time between the data and the rising edge of sclk. t clk 40 period of the clock. t s 5 setup time between cs and sclk. t h 2 hold time between cs and sclk. t hi 16 minimum period that sclk should be in a logic high state. t lo 16 minimum period that sclk should be in a logic low state. t dis_sdo 10 minimum time it takes the sdo pin to switch between an output and a high impedance node, relative to the rising edge of sclk. don?t care don?t care don?t care don?t care sdi don?t care sdo sclk cs t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 don?t care d5 d4 d3 d2 d1 d0 output driver off output driver on sclk t dis_sdo 10992-022
AD8284 data sheet rev. b | page 20 of 28 memory map reading the memory m ap table each row in the memory map table has eight address locations. the memory map is roughly divided into three sections: the chip configuration registers map (address 0x00 and address 0x01), the device i ndex and transfer registers map (address 0x04 to address 0xff), and the adc channel functions registers map (address 0x08 to address 0x2c). the leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. the bit 7 (msb) column is the start of the default hexadecimal value that is given. for example, address 0x09, the global_ clock register, has a default value of 0x01, meaning that bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 0 of this address followed by writing 0x01 to the sw transfer bit in register 0xff, the duty cycle stabilizer is turn ed off. it is important to follow each writing sequence with a write to the sw transfer bit to update the spi registers. caution all registers except for register 0x00 and register 0xff are buffered with a master slave latch and require writing to the transfer bit. for more information about this and other functions, see the an - 877 application note , interfacing to high speed adcs via spi . logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, bit is cleared is synonymous with bit is set to logic 0 or writing logic 0 for the bit. reserved locations do not write to u ndefined memory except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power - up. default values after a reset, critical registers are automatically loaded with default values. these values are indicated in table 9 , where an x refers to an undefined feature.
data sheet AD8284 rev. b | page 21 of 28 table 9 . memory map register s 1 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value default notes/ comments chip configuration registers 0x 00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 mirror t he nibbles to correctly set lsb - first or msb - first mode , regardless of shift mode. 0x 01 chip_id chip id bits[7:0] ( AD8284 = 0xaa, default) read only the default is a unique chip id, specific to the AD8284 . this is a read - only register. device index and transfer registers 0x ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. channel functions registers 0x 08 global_modes channel a buffer power 0 = p ower off 1 = power on (default) channel b buffer power 0 = power off 1 = power on (default) channel c b uffer po wer 0 = power off 1 = power on (default) channel d buffer pow er 0 = power off 1 = power on (default) channel power - d own 0 = power on (default) 1 = power off x internal power - down mode 00 = chip run (default) 01 = full power - down 11 = reset 0xf0 determines the power - down mode (global). 0x 09 global_clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off (global). 0x 0c flex_mux_control x power down unused channels 0 = pd power - down (default) 1 = power on x 0 = s ignal c hannel (a, b , c , d) on (default) 1 = aux channel on 0 = u se external pins (default) 1 = u se internal registers 0 = a ll channels are off 1= s elected c hannel is on (default) 00 = ch annel a (default) 01 = ch annel b 10 = ch annel c 11 = ch annel d 0x04 sets which mux input channel is in use and whether to power down unused channel s . 0x 0d flex_test_io user test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test mode see table 10 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn sequence long 0110 = pn sequence short 0111 = one - /zero - word toggle 1000 = user input 1001 = 1 - bit /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the output_mode register) 0x00 when this register is set, the test data is placed on the output pins in place of normal data. (local , except for pn sequence.)
AD8284 data sheet rev. b | page 22 of 28 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value default notes/ comments 0x 0e test_register enable analog outputs (apout, anout) 0x01 = analog output enabled 0x00 routes the differential output of the aaf to apout and anout . 0x 0f flex_channel_input filter cutoff frequency control 00000 = 1.25 1/4 f samplech 00001 = 1.1875 1/4 f samplech 00010 = 1.125 1/4 f samplech 00011 = 1.0625 1/4 f samplech 00100 = 1.0 1/4 f samplech 00101 = 0.9375 1/4 f samplech 00110 = 0.875 1/4 f samplech 00111 = 0.8125 1/4 f samplech 01000 = 0.75 1/4 f samplech 0100 1 to 01111 = reserved 10000 = 1.25 1/3 f samplech 10001 = 1.1875 1/3 f samplech 10010 = 1.125 1/3 f samplech (default) 10011 = 1.0625 1/3 f samplech 10100 = 1.0 1/3 f samplech 10101 = 0.9375 1 /3 f samplech 10110 = 0.875 1/3 f samplech 10111 = 0.8125 1/3 f samplech 11000 = 0.75 1/3 f samplech 1 100 1 to 11111 = reserved x x x 0x90 low - pass filter cutoff (global). f samplech = adc sample rate. note that the absolute range is limited to 9 mhz to 15 mhz. 0x 10 flex_offset x x 6 - bit lna offset adjustment 00 0000 for lna offset low 10 0000 for lna offset mid (default) 11 1111 for lna offset high 0x20 lna force offset correction. 0x 11 flex_gain_1 x x x x x 000 = 17 db 001 = 17 db 010 = 17 db 011 = 23 db 100 = 29 db (default) 101 = 35 db 0x04 total lna + pga gain adjustment (local) . 0x 12 flex_bias_current x x x x x x lna bias 00 = high (default) 01 = mid to high 10 = mid to low 11 = low 0x00 lna bias current adjustment (global). 0x 14 flex_output_mode x x x x x 1 = output invert (local) 0 = offset binary 1 = twos comple - ment (default) 0x01 configures the outputs and the format of the data. 0x 15 flex_output_adjust 0 = enable data bits [11:0] 1 = disable data bits [11:0] x x x output drive current 0000 = low 1111 = high (default) 0x0f s elect s output drive strength to limit the noise added to the channels by output switching. 0x 18 flex_vref x 0 = internal reference (default) 1 = external reference x x x x internal reference adjust 00 = 0.625 v 01 = 0.750 v 10 = 0.875 v 11 = 1.000 v (default) 0x03 select internal reference (recommended default) or exter - nal reference (global); adjust internal refer - ence. 0x 19 flex_user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined p attern 1 , lsb. 0x 1a flex_user_patt1_ msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined p attern 1 , msb.
data sheet AD8284 rev. b | page 23 of 28 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value default notes/ comments 0x 1b flex_user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined p attern 2 , lsb. 0x 1c flex_user_patt2_ msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined p attern 2 , msb. 0x 2b flex_filter x enable automat ic low - pass tuning 1 = on (self clearing) x x x x x x 0x00 enables low - pass filter tuning 0x 2c ch_in_imp saturation detector limit adjust 00 0 = 1.90 v p - p at pga output 011 = 2.00 v p - p at pga output (default) 11 1 = 2.15 v p - p at pga output other values reserved (001, 010, 100, 101, 110) sat ura - tion detect h ysteresis 0 = low hyste resis (25 mv nominal at pga output) (default) 1 = h igh hyste resis (nominally 60 mv at pga output) x x x input imped - ance 0 = 200 1 = 200 k (default) 0x61 saturation detector adjustment and i nput impedance adjust ment (global). 1 x = undefined feature. table 10 . flexible output test modes 1 output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 same yes 0010 +full - scale short 1111 1111 1111 same yes 0011 ?full - scale short 0000 0000 0000 same yes 0100 checkerboard output 1010 1010 1010 0101 0101 0101 no 0101 pn sequence long n/a n/a yes 0110 pn sequence short n/a n/a yes 0111 one - /zero - word toggle 1111 1111 1111 0000 0000 0000 no 1000 user input register 0x19 and register 0x1a register 0x1b and register 0x1c no 1001 1 - bit /0 - bit toggle 1010 1010 1010 n/a no 1010 1 sync 0000 0011 1111 n/a no 1011 one bit high 1000 0000 0000 n/a no 1100 mixed bit frequency 1010 0011 0011 n/a no 1 n/a means not applicable.
AD8284 data sheet rev. b | page 24 of 28 application circuit s figure 23 . differential inputs 3.3v dvdd33spi 0.1f dvdd33clk 0.1f dvdd33drv 0.1f dvdd33drv 0.1f 1.8v avdd18 0.1f avdd18 0.1f avdd18adc 0.1f 3.3v avdd33ref 0.1f avdd33 0.1f avdd33 0.1f 1.8v dvdd18 0.1f dvdd18clk 0.1f ina+ 0.1 f ina? 0.1 f inb+ 0.1 f inb? 0.1 f ind+ 0.1 f ind? 0.1 f inc? 0.1 f inc+ 0.1 f pdwn sclk aux sdo sdi mux[1] mux[0] cs zsel clk+ clk? 0.1 f 1f 10k? 1% nc nc nc nc nc AD8284 t op view (not to scale) nc nc sflag pdwn dvdd18 sclk sdi sdo cs aux mux[0] mux[1] zsel test1 test2 dvdd33spi nc nc dvdd33drv d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 dvdd33drv d1 d0 nc nc nc agnd avdd18adc test3 anout apout rbias vref band avdd33ref dvdd33clk clk? clk+ dvdd18clk test4 nc avdd18 nc avdd33 ina+ ina? inb+ inb? inc+ inc? ind+ ind? avdd33 inadc+ inadc? avdd18 nc notes 1. all capacitors for supplies and references should be placed close to the part. 2. tie the exposed pad on the bottom side to the analog ground plane. 10992-023 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 nc nc nc nc d0 d11 sflag inadc? avdd18 inadc+ avdd18
data sheet AD8284 rev. b | page 25 of 2 8 figure 24 . single - ended inputs 3.3v dvdd33spi 0.1f dvdd33clk 0.1f dvdd33drv 0.1f dvdd33drv 0.1f 1.8v avdd18 0.1f avdd18 0.1f avdd18adc 0.1f 3.3v avdd33ref 0.1f avdd33 0.1f avdd33 0.1f 1.8v dvdd18 0.1f dvdd18clk 0.1f ina+ 0.1 f inb+ 0.1 f ind+ 0.1 f inc+ 0.1 f pdwn sclk aux sdo sdi mux[1] mux[0] cs zsel clk+ clk? 0.1 f 1 f 10k? 1% nc nc nc nc nc AD8284 t o p view (not to scale) nc nc sflag pdwn dvdd18 sclk sdi sdo cs aux mux[0] mux[1] zsel test1 test2 dvdd33spi nc nc dvdd33drv d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 dvdd33drv d1 d0 nc nc nc agnd avdd18adc test3 anout apout rbias vref band avdd33ref dvdd33clk clk? clk+ dvdd18clk test4 nc avdd18 nc avdd33 ina+ ina? inb+ inb? inc+ inc? ind+ ind? avdd33 inadc+ inadc? avdd18 nc notes 1. resistor r (inx? inputs) should match the output impedance of the input driver. 2. all capacitors for supplies and references should be placed close to the part. 3. tie the exposed pad on the bottom side to the analog ground plane. 10992-024 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 nc nc nc nc d0 d11 sflag inadc? avdd18 inadc+ avdd18
AD8284 data sheet rev. b | page 26 of 28 packaging and ordering information outline dimensions figure 25. 64-lead thin quad flat package, exposed pad [tqfp_ep] (sv-64-5) dimensions shown in millimeters ordering guide model 1, 2, 3 temperature range package description package option AD8284wcsvz ?40c to +105c 64-lead tqfp_ep, waffle pack sv-64-5 AD8284wcsvz-rl ?40c to +105c 64-lead tqfp_ep, 13 tape and reel sv-64-5 1 z = rohs compliant part. 2 w = qualified for auto motive applications. 3 compliant to jedec st andard ms-026-acd-hd. automotive products the AD8284wcsvz models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; ther efore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are a vailable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for these models. compliant to jedec standards ms-026-acd-hd 02-28-2013-a 49 64 1 17 16 32 33 48 49 64 17 1 16 32 33 48 0.50 bsc lead pitch 6.64 bsc sq 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 7 3.5 0 0.15 0.05 0.08 coplanarity view a rotated 90 ccw 1.05 1.00 0.95 0.20 0.09 view a top view (pins down) pin 1 1.20 max seating plane 0.75 0.60 0.45 1.00 ref 0.27 0.22 0.17 bottom view (pins up) exposed pad
data sheet AD8284 rev. b | page 27 of 28 notes
AD8284 data sheet rev. b | page 28 of 28 notes ?2012C2013 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10992-0-7/13(b)

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